Shock Value B/Circuit Lab C Question Marathon

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Bozongle
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Re: Shock Value B/Circuit Lab C Question Marathon

Post by Bozongle »

Alrighty then! More electromagnetism!

Summarize how a conventional doorbell works.
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Re: Shock Value B/Circuit Lab C Question Marathon

Post by 1nxtmonster »

In answer to doorbell:

An electromagnetic solenoid pushes a rod into a sound bar which produces a "DING" sound. When you let go, a spring pushes the piston back to another sound bar which makes a "DONG" sound.

Competition tomorrow, wanna get first this year. Last year got second B/C of tie breaker on total time of circuit building.
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Re: Shock Value B/Circuit Lab C Question Marathon

Post by Toms_42 »

I will try and revive this: Explain the structure of simple inary adders (full adders, half adders, etc) and how they can be assembled togethor to add large numbers.
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Re: Shock Value B/Circuit Lab C Question Marathon

Post by plaid suit guy2 »

I'm surprised no one else answered this. It is a rather simple concept that can be rather difficult to describe, but I got bored. This has not been checked for errors.
Each number's digits could be pushed straight into the adder registers in parallel or multiplexed and sent to the adder serially, the difference then is how the adder times things. 
Each number is comprised of digits, and each of these digits holds a place counted from right to left (one's digit is first, two's digit is second, four's digit is third), digit pairs are digits that hold corresponding places in the two addends. These pairs are what are actually added.

Each digit pair is partially summed by half adders with inputs a and b and outputs s = a b' + a' b and carry c = a b
If the input is in parallel, then the digits for each number each get their own individual line to the adder, if they are summed in series, then the digits are paired up and sent along a single line, where they are read sequentially. Timing is essential for the serial addition, while two registers are needed for parallel addition.
Serial inputs are varied and difficult to describe. They also are unlikely to appear on the test. Parallel input adders are described in the following. Note that the methods is the same for both, but the serial adders do not necessarily need the large number of half adders, one could actually get away with two if done right, they also do not need as much memory inherent to their operation as parallel adders, the downside is that serial adders are usually slower.
Parallel operation with simple carry look ahead is as follows.
There are two layers of half adders. The first layer has the same number of adders as the word size of the registers, the second layer has one less.
The lowest half adder (one's digit) in the first layer has the "s" output sent directly to the output register as the lowest digit. The following adders send their "s" output to the respective b inputs of the second layer. The second layer adders have "s" outputs and "c" outputs. The "s' outputs are pushed directly to their respective digit in the output register, the "c" outputs are OR'ed with the "c" outputs of the corresponding digits of the previous layer and pushed to the "a" input of the next digit adder in the second layer. The lowest adder in the first layer simply pushes the "c" output to the "a" input of the lowest adder in the second layer. The highest adders have their "c" outputs OR'ed and pushed to the overflow register.

In short, if the first layer "s" and "c" were put to numbers, the process would go as follows

Two numbers 10111101 and 10100110 are to be added 
The partial sum at the first layer will be 00011011 and the carry sum will be 10100100.
Bit shift the carry sum to 101001000 and then add it to the partial sum 

There will be carries from this add process as well, but binary addition has a property that if there was a high carry digit in this sum, the next carry digit of the previous sum will be low, so at no time will the same digit carry twice (this is why there aren't as many layers in the adder as the word length). This is a very simple look ahead that most architectures realize. These additional carries are OR'ed into the next carry digit of the first carry number, and this carry look ahead is what is actually summed across s, therefore, the carry sum will be found at the same time as the final sum and the carry value.
The lowest place in the partial sum will never have a carry sum, so the one's digit of the final number is the same. In this case, it is 1. 
The carry sum 10100100 will be added to the partial sum starting at the lowest digit, giving 1,01010011 and an additional (shifted) carry of 000010000, so the final sum actually comes from the OR'ed values of this carry with the previous carry (which has a zero in that location) 101011000, and the partial sum 00011011, taken at each digit from the lowest to highest so as to prevent reiteration. 
The process will go like this

  
[color=#FFFFFF]__[/color]10111101
[color=#FFFFFF]_[/color][u]+10100110[/u]
[color=#FFFFFF]__[/color]00011011
[u]+101001000[/u]
[color=#FFFFFF]_________[/color]1
[color=#FFFFFF]________[/color]1
[color=#FFFFFF]_______[/color]0
[color=#FFFFFF]______[/color]0
1or0=1
[color=#FFFFFF]__[/color]00011011
[u]+10101____[/u]
[color=#FFFFFF]_____[/color]0
1+0=1
[color=#FFFFFF]__[/color]00011011
[u]+1011_____[/u]
[color=#FFFFFF]____[/color]1
[color=#FFFFFF]___[/color]1
[color=#FFFFFF]__[/color]0
[u]_1________[/u]
[u]1_01100011[/u]
Assuming an 8 bit word length, there is a 1 in the overflow register, so the resultant number will take two memory spaces as 00000001,01100011.
It is also worth noting that no computer can simultaneously add more than two numbers, but rather, they take the sum of two, then add that sum to the next number and repeat.
Describe an effective method of binary multiplication
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Nationals 2012:
Sound of Music: 8th

Nationals 2013:
Remote Sensing: 1st
ELG: 1st
MagLev: 6th

State 2014:
Boomi: 1st (scored 1824)
Circuits: 1st
Compound: 3rd
Malgev: 1st
MP: 2nd

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